1. Field of the Invention
The present invention relates in general to a method to protect MOS components and the apparatus thereof. In particular, the present invention relates to a method to protect MOS components from antenna effect and the apparatus thereof.
2. Description of the Related Art
During plasma etching, damaging induced by plasma to the MOS component are referred to as plasma charging damaging, or antenna effect. Due to the uneven distribution characteristics of charges in plasma, charges are accumulated on the conductors (such as: polysilicon or aluminum alloys) with large surface areas or long sides. The charges generate an electric field on the gate oxide layer of the MOS component. When enough charges are collected, the electric field across the gate oxide layer changes the properties of the MOS component. More severe damage may occur if the current is high enough to pass through the gate oxide layer.
FIG. 1 shows a conventional circuit design using a diode to reduce the antenna affect. In FIG. 1, T1 is a MOS component in an integrated circuit (IC), the substrate (or bulk) B of the MOS is coupled to its own source, or to a fixed power rail (VDD or VSS). The diode D1 has its anode coupled to the substrate of the IC. It is assumed that the conductive line L1 connected with the gate of the MOS component T1 has a very large surface area or periphery length. Due to the plasma characteristics, a large amount of charges is accumulated on the conductive line L1, causing the antenna affect (as the antenna Ana shown in FIG. 1).
If the accumulated charges are negative charges, the diode D1 provides a discharge path to release the negative charges to the substrate sub1 of the IC, preventing damaging made to the gate oxide layer of the MOS component T1. However, when the accumulated charges are positive charges, no discharge path exists. The electric field across the gate oxide layer thus degrades the layer. Moreover, the large stray capacitance of the diode D1 compromises the operating rate of the IC circuit, resulting in slower operating speeds.
FIG. 2 shows a conventional circuit design using a transmission gate to reduce the antenna effect. In FIG. 2, the conductive line L2 connected to the gate of the MOS component T2 has very a large area or is very long. Due to the plasma distribution characteristics, large amounts of charges are accumulated on the conductive line L2, causing the antenna effect (as the antenna Ana shown in FIG. 2). Herein, T2 is the MOS component of a IC circuit with its substrate B connected to the source or a fixed power rail (VDD or VSS).
To reduce the antenna effect, a transmission gate is placed in the IC circuit in FIG. 2 and coupled with the gate of the MOS component T2. In the NMOS transistor NT of the transmission gate, the gate and the substrate are respectively coupled to the nodes VDD and VSS In the PMOS transistor PT of the transmission gate, the gate and the substrate are respectively coupled to the nodes VSS and VDD. Irrespective of whether the accumulated charges in the antenna effect are of either of the bias polarities, they are discharged through the parasitic diodes between the source/drain and the substrate of the NMOS transistor NT (or PMOS transistor PT) to prevent the MOS component T2 from degradation.
Because the transmission gate is located on the path for controlling the gate of the MOS component T2, and the transmission gate has parasitic capacitor C and resistance R, the RC constant will lead to the delay of the control signal sent to the gate of T2 and compromise the operating rate of the MOS component T2. To enhance the operating rate of the MOS component T2, resistance R is expected to be reduced. The easiest way to reduce the resistance R is to cut the channel length or increase the channel width of the transmission gate. However, by doing so, the capacitance C is simultaneously increased. Therefore, it is awkward to reduce the antenna effect by adjusting the R and C values according to the configuration in FIG. 2.